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IPS Featured Publication
A new merged metallic and adhesive, low-temperature bonding technique was developed for 3D integration.
Featured Publication
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CADTS Featured Publication
A fabricated 3D logic-DRAM SoC chip demonstrates parallel memory accesses to alleviate pin count pressure.
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DS Featured Publication
Multi-gate In(0.7)Ga(0.3)As quantum well FETs are simulated, fabricated, and characterized in detail.
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CADTS Featured Publication
New SAT solver solves 33% more benchmarks than nearest state-of-the-art technique.
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CADTS Featured Publication
New variation aware electromigration evaluation tool points designers to critical chip areas to be improved.
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DS Featured Publication
Physically based TCAD was developed for hot-carrier-stress degradation prediction in lateral DMOS transistors.
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IPS Featured Publication
A suite of critical modeling tools were developed to design and scale plasma equipment and processes.
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SRC Celebrates its 30th Anniversary
Thirty years of collaborative research leadership in semiconductor and related technologies.
Article
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MIT: Self-assembling Structures Align Wires, Bends and Junctions
Researchers at MIT have found a new way of making complex three-dimensional structures using self-assembling polymer materials that form tiny wires and junctions.
SRC In The News
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SRC and Stanford University Prove New Circuit Pattern-Design Process, See Promise for 14 Nanometer Design with Directed Self-Assembly
Unprecedented Accuracy for Placement of Contact Holes Helps Chip Industry Push Back Costly Migration to EUV Lithography
Press Release
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CADTS Featured Publication
New probing technique for pre-bond TSV test retains high test clock frequency and only 1-2% area overhead.
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IPS Featured Publication
Ce-based Pb-free solder exhibits superior oxidation and tin whiskering characteristics compared to SAC alloys.
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IPS Featured Publication
A definitive study and optimization of TSV's was done, and design guidelines and models were developed.
Featured Publication
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